In a semiconductor integrated circuit (IC) fabrication process, the back end of line (BEOL) processing results in a plurality of interconnects comprising alternating metal (e.g., copper) and inter-layer dielectric (ILD) layers, with vias through the ILD layers connecting the metal layers.
In a typical BEOL conductive via fabrication process, copper (Cu) gap filling was performed by electrochemical deposition (ECD) in a substrate formed by plasma vapor deposition (PVD) of a Cu seed layer. When applying these techniques to advanced technologies, such as the 45 nanometer node, post ECD bottom voids can be observed within the PVD Cu seed due to seed layer discontinuities. The observed discontinuous seed layer may be caused by thin seed or Cu oxide dissolving when in contact with the acidic ECD solution.
When exposed to air, a metal surface such as Cu may be oxidized to form a metal oxide, which adversely impacts subsequent processing. For example, the PVD Cu seed layer, when expose to air, is oxidized to form CuO prior to Cu electrochemical deposition (ECD). A typical ECD solution (the electrolyte) is an acid, which contains from about 1% to about 50% H2SO4 or Methanesulfonic acid. In such an acidic solution, Cu oxide is dissolved, and the Cu seed layer might become discontinuous.
Exposure of metal to air during processing may adversely affect the fabrication process in other ways, such as affecting a metal cap layer. In determining the performance of a BEOL processing technology, a variety of criteria are used, including the maximum current density (Jmax), the line resistance Rs, and the stress migration (SM). As semiconductor IC technology migrates from 90 nanometer technology to smaller feature sizes, the desired maximum current density Jmax increases. Therefore, a method to improve the electromigration (EM) is desired.
A metal cap layer can be selectively deposited over the exposed metal surfaces. It has been demonstrated that a tenfold improvement of electromigration (EM) performance in the (VxMx, VxMx+1) interconnect can be obtained by selective use of the metal cap on copper lines. One approach includes deposition of a cobalt cap.
After chemical mechanical polishing (CMP), the cap layer is selectively applied over the metal lines, but not over the dielectric. After CMP, there is copper oxide on top of the copper line, some post CMP residue on the dielectric, and/or organic contamination from the CMP on both the dielectric and the copper surface. To uniformly deposit a selective metal cap layer on the Cu surface, the Cu oxide must be removed. A pre-clean step has been used to remove the copper oxide. One conventional method includes a wet clean process of immersing the wafer in an acidic solution to dissolve Cu oxide. For example, to achieve high selectivity performance (to avoid leakage), a wet clean solution, including H2SO4, Citric Acid and a wetting agent, has been applied to the substrate having exposed metal and dielectric surfaces. The H2SO4, Citric Acid and wetting agent remove metal oxide on the metal surface, metal residue on the dielectric surface, and organic residues on both the metal and dielectric surfaces.
However, during Cu oxide removal by the above-described acidic solution, a recess is created, which results in an increase in line resistance. For example, in some cases, after the metal oxide has been removed, a 3% to 5% increase in line resistance Rs has been observed. For example, the line resistance increase for a process including deposition of a cobalt cap has been measured at about 2.4%. An increase in Rs degrades RC signal delay performance. Also, because the Cu oxide formation can be pattern dependent, differences in the depths of the Cu recess occur on dense and iso pattern areas, resulting in non-uniform metal cap deposition.